Headquarters: Kraków, Poland
DATAmundi.ai is preparing for an upcoming large-scale dataset project. We expect to onboard approximately 50–100 experts within a short timeframe.
To support smooth and efficient launch, we are expanding our expert pool in advance.
Who We Are Looking For
Individuals with knowledge or studies in:
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digital systems,
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hardware design,
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digital logic and electronics,
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FPGA/ASIC fundamentals,
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HDL languages (Verilog / SystemVerilog preferred; VHDL optional)
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Proficiency in English sufficient to follow instructions and communicate clearly.
Ideal profile: recent graduates of technical fields or enthusiasts with relevant practical experience.
Project Overview
The project involves creating a dataset of diagram images paired with one of two types of technical artefacts:
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Diagram + HDL code (Verilog/SystemVerilog)
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Diagram + English technical explanation of the diagram
Workload distribution: 50% code-based, 50% description-based.
The required diagram types include:
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circuit diagrams,
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timing diagrams (waveforms),
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state diagrams (finite state machines).
(With a near-even distribution across all three categories.)
Additional requirements:
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At least 60% gate-level diagrams
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No more than 30% simple diagrams
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Topics include processors, memory components, digital circuits, and standard protocols (e.g., AMBA AXI).
Conditions
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Estimated hourly rate: ~20 USD/h
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Fully remote, candidates can be located anywhere
Flexible work, but availability should support handling high task volumes.
To apply: https://weworkremotely.com/remote-jobs/summa-linguae-technologies-digital-design-diagram-creators
